Code selectors for selective calling systems



R. C. CLARK CODE SELECTORS FOR SELECTIVE CALLING SYSTEMS Original FiledOct. 10, 1958 3 Sheets-Sheet 1.

F 06.7 F|G.l RING COUNTER 7 E A B C D E RING COUNTER Q A B C D -|4Q I4I, H I g I4I AND AND 6 8 I I f ADVANCE DRIVER OR l5 5 ON 9 l0 Is ABLEINHIBIT CLOCK SWITCH g GATE ALARM ENABLE f ENABLE ON N 3 2 ghfifDIFFERENTIATOR INVERTER OFF 3 I F- E IB T IB'IT IBIIT IBIT F |G.3 E q'CLOCK PULSES RECEIVED (NO u llll IIIII lloll lllll INVERTED i CODE Vn u3 3 OUTPUT OF STAGEA 3-4 OUTPUT 0F STAGEB L 3-5 OUTPUTOF STAGEC OUTPUT0F STAGE D 3-7 ovluou I 3-8 -3V.i

START "I ll "0" lloll INVENTORI ROBERT C. CLARK,

HIS ATTORNEY.

Aug. 8, 1967 R. c. CLARK CODE SELECTORS FOR SELECTIVE CALLING SYSTEMSOriginal Filed Oct. 10, 1958 3 Sheets-Sheet INVENTOR- ROBERT C. CLARK,

HIS ATTORN Y.

3, 1967 R. c. CLARK 3,335,406

CODE SELECTORS FOR SELECTIVE CALLING SYSTEMS Original Filed Oct. 10,1958 3 Sheets-Sheet 3 FIG.4 A B C D sTART STOP DELAY fififi swITcI-I D(.QsBITI ON 7 '20 L I I043 f] IIo I08 I09 9 BISTABLE DELAY H7 SWITCHCLOCK LINE QR OFF f T OFF ON 1 H6 I2I- AND 91+ INVERTER CLOCK IIIBIsTABLEII5F AND I DIFFERENTIATOR SWITCH OFF swITcI-I 4 H3 ALARM I23 I2}I24 ON I07 OFF DELAY LINE INTERVAL INTERVAL F IG 5 START INTERVAL CODE0\/- INPUT START Ill" 1 III" "on n INVERTER DIFFERENTIATOR OUTPUT CLOCKPULSES ,L [L 5-3 DELAY swITcH A [L INPUT DELAY IL A 5 5 swITcI-I OUTPUTBISTABLE s s SWITCH? OFF l3| IOZFIG.6 INVENToR: 1 INVERTER @ROBERT K, lBY KL 27 lO M HIS ATTORNEY.

United States Patent 3,335,406 CODE SELECTORS F R SELECTIVE CALLINGYSTEMS This invention relates to communication systems, and, moreparticularly, is concerned with code selectors for selective callingsystems, and is a division of application Ser. N0. 765,423, filed Oct.6, 1958, now Patent N0. 3,166,735, granted Ian. 19, 1965, in the name ofRobert C. Clark and assigned to the assignee of the present invention.

Various systems have heretofore been proposed in the prior art forpaging doctors or other persons who move from place to place and whootherwise could not be contacted. Such a system must have a receiverwhich is small enough to fit into the pocket of the person who is to becalled. This receiver must have a selector capable of actuating an alarmin response to only the transmitted code designated for that particularreceiver. Additionally, the selector must perform its decoding functionsreliably and without error.

Prior art selective calling systems have used selectors in which avibrating reed actuates an alarm in response to the reception of aparticular radio frequency. These selectors have the disadvantage ofrequiring the use of a separate frequency in the already over-crowdedradio frequency spectrum to page each selector. This disadvantage hasbeen overcome in this invention by making each selector responsive to abinary code made up of the presence or absence of a single radiofrequency.

Prior art selectors, which have attempted to make use of a binary codeto page the selector, have been so complex as to make their useprohibitive. These selectors have attempted to store the received codein a shift register or a binary counting chain until the received,stored code can be compared with the code which the selector is designedto recognize. This invention avoids much of the complexity necessary ina selector which stores a complete received code by sampling the code asit is received to determine any errors between the received code and thecode which the selector is designed to recognize. A single error in thereceived code is stored to prevent actuation of an alarm which indicatesthat the selector has been paged.

It is accordingly an object of this invention to provide an improvedselector for a selective calling communication system by means of whichone of a plurality of receivers can be paged.

Another object of this invention is the'provision of an improved codeselector for actuating an alarm in response to only one of a pluralityof received codes.

Another object of this invention is the provision of a code selectorhaving a size small enough to conveniently fit into the pocket of theperson who carries the receiver.

Another object of this invention is the provision of a code selectorwhich will perform its function reliably and accurately.

Another object of this invention is the provision of a code selectorwhich utilizes a code requiring only a single radio frequency.

Still another object of this invention is the provision of a codeselector of simplified construction.

These and other objects of the invention, which will become apparent asthe description proceeds, are achieved in one form of my invention byproviding a completely transistorized code selector which decodesinformation 3,335,4h6 Patented Aug. 8, 1967 which is transmitted in theform of binary code groups. The code identifying a particular receiverconsists of a number of binary bits.

Binary codes, each identifying a particular receiver, are received byall receivers. The first bit of each code is a start bit which enables aclock circuit in the selector to drive a ring counter through onecomplete cycle. This ring counter has a number of stages, each of whichcorresponds to one bit of the received code. As the ring counter isdriven through its cycle, gating circuitry compares the output of eachstage of the ring counter with the corresponding bit of the receivedcode. If there is a coincidence between the binary code, which theselector is designed to recognize, and the incoming binary code, analarm is actuated at the end of the ring counter cycle. However, if thegating circuitry detects a difference between any bit of the receivedcode and the corresponding bit of the code which the selector isdesigned to recognize, the gating circuitry will store the error toinhibit the actuation of the alarm at the end of the ring counter cycle.

The received code may be decoded in the selector by a technique commonlyknown as amplitude sampling or by another technique known as transitionsampling. Both of these techniques will be described in thisapplication.

For a better understanding of the invention, reference should be made tothe accompanying drawings wherein:

FIG. 1 is a block diagram of the selector of the subject invention.

FIG. 2 is a schematic drawing of the block diagram of FIG. 1.

FIG. 3 (1 through 8) shows waveform diagrams depicting the operation ofthe selector of FIG. 1.

FIG. 4 is a block diagram of a modification of the selector of thesubject invention.

FIG. 5 (1 through 6) shows waveform diagrams depicting the operation ofthe selector of FIG. 4.

FIG. 6 is a schematic drawing of the inverter-differentiator shown inblock form in FIG. 4.

FIG. 7 is a fragmentary illustration of a code selector incorporating aconference code modification.

FIGS. 1 and 2 show a selector which decodes the received code by theamplitude sampling technique. The outputs of the ring counter stages aresuccessively compared with the corresponding received bit or with thecorresponding inverted received bit of the code to de termine whetherthe received code is the same as the code which the selector is adaptedto recognize. Two AND circuits are used to compare the outputs of thering counter stages with the received or inverted bits.

Referring particularly to FIG. 1, there is shown a receiver line 1 uponwhich the incoming binary code is impressed. The binary code is made upof a number of binary bits, each bit consisting of one of two giveninput conditions Which are referred to herein as the 1 and 0 states. Inthe subject embodiment, the 1 state is a 3 v. condition while the 0state is a 0 v. condition. The first bit of the code is a binary 1 whichis inverted in the inverter 2 and difierentiated in the differentiator3. The differentiated 1 turns on the clock switch 4. The clock switchenables a clock 5. The clock, together with the advance driver 6,produces pulses having the same time spacing as the spacing between thebits of binary information in the incoming binary code. These clockpulses drive a ring counter 7. The ring counter, of a type well-known inthe art, has, in the form shown, four magnetic core binary storageelements A, B, C and D. A binary 1 is stored in the first stage, A,before the binary code is received. This binary 1 is driven tosucceeding stages of the ring counter by the clock pulses.

When the binary l, which is driven to succeeding stages by the clockpulses, is driven from stage D, a pulse is transferred by the trip line8 through the inhibit gate 9, to the alarm 10. Actuation of the alarmindicates that the proper binary code has been received by the selector.

Gating circuitry 11 is provided to detect the presence of a code otherthan the code which the selector has been designed to recognize, and toinhibit the actuation of the alarm through the bi-stable switch 12 andthe inhibit gate 9. The gating circuitry shown has been arranged torecognize the binary code 1101. This gating circuitry consists of an ANDcircuit 14 connected to stages A, B and D, and another AND circuit 13connected to stage C. The incoming code from receiver line 1 is alsoconnected to AND circuit 13 through the inverter 2. The incoming code onreceiver line 1 is directly connected to the AND circuit 14. The outputsof both AND circuits 13 and 14 are connected to the OR circuit 15. Theoutput of OR circuit 15 is connected to turn on the bi-stable switch 12.

Before attempting a comprehensive description of the operation of theselector of FIG. 1, the operation of each of the circuits, shown inblock form in FIG. 1, will be described with reference to the schematicdrawing, FIG. 2.

The inverter 2 is formed of a transistor 16 and associated components.The receiver line 1 is connected to the base of transistor 16 through aresistor 35, and the collector of the transistor 16 is connected to -12v. through a resistor 17. When the receiver 1 is at volt, the transistor16 is nonconducting, and the output of the inverter, which is connectedto the collector of the transistor 16, will be at l2 v. because of the--12 v. potential connected to the collector. When the receiver line 1is at -3 v. condition, corresponding to a binary 1, the transistor willconduct, and the output of the inverter will be at the 0 v. level. Thus,the inverter 2 will invert each received bit to produce a correspondinginverted bit at the output.

The output of the inverter is ditierentiated in the differentiator 3,which consists of a resistor 18 and a capacitor 19. A diode 20, tied tothe alarm through the resistor 21, merely serves as an AND gate toprevent passage of a pulse from the inverter 2 through thedifferentiator 3, when the alarm 10 has been actuated.

The output of the ditierentiator is fed through a capacitor 22 to theclock switch 4 and more specific-ally to the base of a transistor 23which, together with a transistor 24 and associated circuitry, forms theclock switch 4. The collector of transistor 23 is connected to the baseof transistor 24 through a resistor 56 and the collector of transistor24 is connected to the base of transistor 23 through a resistor 57. Thebase electrodes of transistors 23 and 24 are connected to 12 v. and 0v., respectively, through biasing resistors 53 and 54. The emitters oftransistors 23 and 24 are connected to 12 v. and 0 v., respectively,through diodes 58 and 59. The transistors 23 and 24 are normallynonconducting. A positive pulse on the line from the ditferentiator tothe base of transistor 23 will switch transistors 23 and 24 from thenonconducting, or OFF, state to the conducting, or ON state. Thepositive pulse on the base of transistor 23 allows transistor 23 tocon-duct, thus lowering the collector voltage toward the 12 v. which isconnected to the emitter. The negative voltage on the collector, whichis connected to the base of transistor 24, causes this transistor toconduct. When conducting, the collector voltage of the transistor 24will rise toward the 0 v. level of the emitter. This positive-goingvoltage on the collector of transistor 24, which is connected back tothe base of transistor 23, will turn transistor 23 on more fully, thuslocking both transistors 23 and 24 in the ON condition. The transistorswill remain ON until a positive pulse is transferred from the trip line8 through a capacitor 25 and a diode 26 to the base of transistor 24. Apositive pulse at the base of transistor 24 will turn this transistorOFF. The coupling between the collector of transistor 24 and the base oftransistor 23 will turn transistor 23 OFF also. The biasing resistors 53and 54 will hold transistors 23 and 24 in the OFF condition until apositive pulse at the base of transistor 23 turns both transistors ONagain.

The output of the clock switch 4, taken from the collector of transistor24, is connected to the clock 5 through resistors 28 and 29. The clock 5comprises a double base diode 27 and associated circuitry. The collectorof transistor 24 is connected through resistors 28 and 29 to the emitterof the transistor 27. A charging capacitor 30 is connected between theemitter of transistor 27 and -12 v. The base b of the transistor 27 isconnected directly to l2 v. When enabled by the clock switch 4, theclock 5 will oscillate to produce periodic negative clock pulses. Whenthe clock switch 4 is in the OFF condition, the -12 v. on the collectorof transistor 24, which is connected to the emitter of transistor 27,prevents the clock from oscillating. However, when the clock switch isturned ON, the collector of transistor 24 will be switched to 0 v. Thecapacitor 30 will charge toward 0 v. until the potential at the emitterof transistor 27 reaches a point at which transistor 27 will conduct.When transistor 27 conducts, the capacitor 30 will be discharged and anegative pulse will appear at the base b After discharge of thecapacitor 30, the transistor 27 will again be cut OFF until thecapacitor 30 again becomes charged to the potential at which transistor27 will conduct.

Each time the transistor 27 conducts, a negative clock pulse appears atthe base 12 of transistor 27. This negative pulse is coupled through acapacitor 31 to the advance driver 6. This driver consists of thetransistor 32, together with associated circuitry. The negative pulsesat the base of the transistor 32 will allow the transistor 32 toconduct. Each time the transistor 32 conducts, a positive pulse will befed from the collector of the transistor 32 to a magnetic core ringcounter 7.

The ring counter 7 is of a type well-known in the prior art. This ringcounter consists of four bistable storage elements A, B, C and D. Thestorage element A consists of the core 33a having wound thereon anadvance winding 34a, a shift winding 35a, a drive winding 36a, aregenerative winding 37a and an output Winding 38a. The storage elementsB, C and D have corresponding components. The same numerals are employedfor the components of these storage elements, the subscripts b, c and d,respectively, being added.

The advance windings 34a, 34b, 34c and 34d are connected in series withone end being connected to -12 v. and the other end being connected tothe advance driver 6. The regenerative windings 37a, 37b, 37c and 37dare connected in series with one end being connected to 0 v.

and the other end being connected to provide regenerative feedback tothe advance driver 6. One end of the drive winding 36a is connectedthrough a diode 39a and a resistor 58a to one end of the shiftingwinding 35b. Similarly, the drive winding of each stage is connected tothe shift winding of the next successive stage. The drive winding 36d isconnected to the shift winding 35a of storage element A to complete thering as is common in ring counters of this type.

The operation of the ring counter can be described briefly as follows.Clock pulses from the advance driver 6 are applied to the seriesconnected advance windings to drive the cores toward the 0 position.Before the recurrent clock pulses are applied to the advance windings,the first magnetic core 33a has been set in the 1 position. The firstclock pulse will tend to drive this core back to the 0 position and atthe same time a positive pulse will be induced in the drive winding 36a.This positive pulse will be transferred by the diode 39a and theresistor 58a to the shift winding 35b of the magnetic core 33b with apolarity such that the magnetic core 33b will be driven to the 1position. Similarly, the next clock pulse through the advance windingswill drive the magnetic core 3311 back to the "0" position while at thesame time shifting the 1 to the third magnetic core 330. Each clockpulse will transfer the binary 1 to the next succeeding magnetic storageelement. When the binary 1 has reached the last storage element D, thenext clock pulse will transfer the binary 1 to the first magneticstorage element A. This transfer is effected in the same manner as thetransfer of the binary 1'to successive storage elements previouslydescribed. The same clock pulse that transfers the 1 from stage D tostage A will shift stage D back to the state and cause a positive pulseto be transferred from the output winding 38d on core 33d over the tripline 8 through a capacitor 52, to inhibit gate 9. The pulse from outputWinding 38d will also be coupled through the capacitor 25 and the diode26 to the clock switch 4 so as to turn the clock switch 4 OFF. The ringcounter 7 will then have a 1 in stage A, the clock will be turned OFF,and the counter will be in a state to receive the next group of clockpulses. The ring counter has been driven through one complete cycle.

If the selector has been designed to recognize the code 1101, the outputwindings 38a, 38b and 38d are connected in series with one end beingconnected to 0 v. and the other end being connected to AND circuit 14.The output winding 380 has one end connected to 0' v. while the otherend is connected to the AND circuit 13. The arrangement of theconnections of the output windings of the ring counter stages to the ANDcircuits 13 and 14 determines the particular code which the selector isdesigned to recognize.

These connections of the output windings cause a positive pulse to betransferred from the output windings 38a, 38b or 38d to AND circuit 14whenever any one of the stages A, B or D is shifted from the 1 to the 0-state.

The AND circuit 14 consists of a diode 40*, a resistor 41 and acapacitor 42. Positive pulses from the seriesconnected output windingsof stages A, B and D are coupled to the anode of the diode 40' throughthe capacitor 42. These positive pulses will be coupled through thediode 40 only when the other input to the AND circuit, the input fromthe receiver line through the resistor 41 is at 0 v., the 0 state of thereceiver line. Similarly, the AND circuit 13 consists of a resistor 43and a diode 44. Positive pulses from the output winding of stage C willbe coupled through the AND circuit 13 only when the input from theinverter 2 through resistor 43 is at 0 v. The outputs of AND circuits 13and 14, taken from the cathodes of diodes 40 and 44, are connectedtogether to form the OR circuit 15.

The output of the OR circuit 15 is connected through the capacitor 45 tothe bi-stable switch 12. More specifically, the pulse is coupled to thebase of a transistor 46 which, together with a transistor 47, forms thebistable switch 12. This bi-stable switch 12 is normally OFF and will beturned ON by a pulse from the OR circuit 15.

However, the bi-stable switch 12 can be turned ON only when the clockswitch 4 is in the ON position. In order to insure that the transistor47 can conduct only when the clock switch 4 is in the ON position, thecollector of the transistor 24 is connected directly to the emitter oftransistor 47. The transistor 47 can conduct only when the collector oftransistor 24 is at 0 v. This occurs when transistor 24- is in theconducting or ON state. When clock switch 4 is ON, a positive pulse fromeither AND circuit 13 or AND circuit 14 through capacitor 45 to the baseof transistor 46 will turn the bi-stable switch 12 ON. The operation ofbi-stable switch 12 in switching between the ON and the OFF states issimilar to the operation of clock switch 4 previously described. Oncebi-stable switch 12 has been turned ON, it will remain ON until clockswitch 4 is turned OFF, thus returning the emitter of transistor 47 to12 v. and shutting OFF both transistors 46 and 47.

The inhibit gate 9 consists of a diode 60, a resistor 61, and acapacitor 48. Trip line 8 is connected to the inhibit gate 9 and morespecifically to the anode of diode 60 through the capacitor 52. Thebi-stable switch 12 is connected directly to the anode of diode 60'. Apositive pulse from the trip line 8 of the ring counter will passthrough the diode 60 only when the bi-stable switch 12 is in the OFFcondition. If bi-stable switch 12 has been turned ON during theoperation of the ring counter, the pulse will not pass through diode 60'to the alarm 10.

The alarm 10 includes a switch consisting of transistors 49 and 50', andassociated circuitry. The operation of this switch is similar to theoperation of the clock switch which has been already described. Apositive pulse from inhibit gate 9 to the base of transistor 49 willturn the switch O-N. Both transistors 49 and 50 will conduct and anysuitable indicator, which is connected between the collector oftransistor 50 and -12 v., will be actuated.

The operation of the selector of FIGS. 1 and 2, in recognizing theparticular code 1101, can now be described in detail. This can best bedone by referring to the Waveform diagrams in FIG. 3. FIG. 3-1 shows theclock pulses which are fed into the advance windings of the ringcounter. FIG. 32 shows the incoming code on the receiver line 1, andFIG. 33 shows the inverted receiver line output from the inverter 2. Thefirst bit of the code, shown in FIG. 32, is the start bit which enablesthe clock to drive the ring counter. The remainder of the bits, shown inFIG. 32, represent the binary code 1101 which the selector of thesubject embodiment has been designed to recognize.

The first transition from 0 to 1 on the receiver line will turn ON theclock switch 4. The first clock pulse will occur 1.5 bits after thefirst transition, and thereafter clock pulses will occur midway betweenthe transition from one bit to another-on the receiver line. The clockcircuit previously described in detail can be designed so that the firstclock pulse occurs the desired 1.5 bits after the reception of the startbit. The first clock pulse Will shift the first stage A of the ringcounter from the 1 position back to the 0 position. This clock pulsewill induce a positive pulse output on the output winding 38a of core A,as shown in FIG. 34. This positive pulse will be transferred to the ANDcircuit 14. The pulse cannot pass through the AND circuit since theother input to AND circuit 14, the receiver line input, is in the 1 or-3 v. position, as shown in FIG. 3-2. This AND circuit 14- will pass apulse only when the pulse occurs at the same time that the receiver lineinput is in the 0 position. The same first clock pulse has driven thesecond stage of the ring counter B to the 1 position.

The second clock pulse will drive the second stage B to the 0 position,and at the same time induce a positive output pulse on the outputwinding of stage B, as shown in FIG. 35. This output pulse likewise willbe transferred to the AND circuit 14. The output pulse, shown in FIG.35, will not pass through the AND circuit 14 because the receiver lineinput to the AND circuit 14 is still in the 1 position, as shown in FIG.32. This 1 position of the receiver line is the second bit, in theincoming code. The next clock pulse will drive the third stage C fromthe 1 to the 0 position, inducing an output pulse on the output windingof stage C. This output pulse, shown in FIG. 15-6, is transferred to theinput of the AND circuit 13. This pulse will not pass through the ANDcircuit 13 since the other input to the AND circuit 13, the invertedreceiver line input, as shown in FIG. 3-3, is in the 1 position. This 1of the inverted receiver line corresponds to the third bit, 0, in thereceived code 1101.

Similarly, the fourth clock pulse will drive the stage D from the 1position to the 0 position inducing an output pulse on the outputwinding of stage D. This pulse, shown in FIG. 37, will not pass throughthe AND circuit 14 since the receiver line input, FIG. 32, is in the 1position corresponding to the fourth bit, 1, in the incoming code. Sinceno pulses have passed the AND circuits 13 and 14, the bi-stable switch12 has not been turned ON. If this bi-stable switch 12 had been turnedON, the inhibit gate 9 would not pass a pulse. Since position 7 thisgate 9 is not inhibited when the 1 is shifted from the last stage D, thepositive pulse appearing on the output winding will pass through thisgate to actuate the alarm 10. Actuation of this alarm indicates that thecode selector has received the proper binary code input on the receiverline.

A short illustration will indicate the operation of the code selectorwhen a binary code input is received which is one other than the codewhich the selector is designed to recognize. FIG. 3-8 shows a binarycode 1001. This differs from the code which the selector is adapted torecognize in only one bit; the second bit of the code, shown in FIG. 38,is a instead of a 1 as in the desired code. The first clock pulse willproduce a positive output pulse on the output winding of stage A, shownin FIG. 3-4, which will not pass the AND circuit 14 because the receiverline input, FIG. 38, is in the 1 position. However, the second clockpulse will cause an output on the output winding of stage B, shown inFIG. 35, which will pass the AND circuit 14. The receiver line input ofFIG. 38 is in the 0 position since the second bit differs from the codewhich the selector is adapted to recognize. Since the receiver lineinput in the 0 position and the positive pulse from stage B are appliedto the AND circuit 14 simultaneously, the pulse will pass the ANDcircuit 14 and turn the bi-stable switch 12 ON. The bi-stable switch 12will inhibit the gate 9 so that when the last stage D is driven from the1 to the 0 stage, the resultant pulse will not pass through the gate 9to actuate the alarm 10. In a similar manner, whenever one of the binarybits on the incoming receiver line differs from the desired code 1101, apulse will pass through either the AND circuit 13 or the AND circuit 14to turn the bi-stable switch 12 ON and inhibit any actuation of thealarm 10.

Note that, in both illustrations, the same pulse, which is produced atthe output of stage D and is fed to the inhibit gate 10, is alsoconnected to the clock switch 4. This pulse will turn the clock switch 4OFF so that no further clock pulses are fed to the ring counter. Theclock pulse, which drives stage D from the 1 to the 0 stage, alsotransfers the binary 1 to the stage A. The ring counter has been driventhrough one complete cycle, and the selector is in a condition toreceive the next received code.

FIG. 4 shows a selector which utilizes a system of recognizing a singlecode by means of transition sampling rather than the amplitude samplingsystem previously described. The code differs from the code used in theprevious system in that a transition between the two input conditions ina desired interval represents a binary l, and no change in the inputcondition represents a binary 0. The code 1101 is shown in FIG. 5-1. Thefirst transition, shown in FIG. 5-1, is the start transition whichenables the clock to drive the ring counter through its cycle. The firsttransition in the code 1101 occurs two intervals after the starttransition, and thereafter a transition in a particular intervalrepresents a binary 1, and an absence of a transition represents abinary 0.

The selector of FIG. 4 is designed to test for the presence of atransition in an undesired interval and the absence of a transition in adesired interval. It stores a single error, as in the previous example,to prevent an alarm at the end of the code.

The incoming binary code on a receiver line 101, shown in FIG. 5-1, isdifferentiated in an inverter-differentiator 102 so that onlytransitions in the code are fed to the selector. Theinverter-diiterentiator 102 differs from an ordinary difterentiator inthat it will produce a positive output pulse whenever there is apositive or a negative-going tranistion in the input. FIG. 6 shows theinverter-differentiator 102 in detail. The input code, shown in FIG.5-1, is differentiated by a capacitor 126 and a resistor 127. Positivetransitions pass through a diode 128 to an output 129. Negativetransitions are inverted in an inverter 130 8 and pass through a diode131 to the output 129. There will be a positive output pulse at 129,shown in FIG. 5-2, whether there has been a positive or a negativetransition in the code.

Since the other circuit elements, shown in block form in FIG. 4, havebeen described in detail in conjunction with the previous embodiment, nofurther attempt will be made to explain the details of the circuits.

Referring back to FIG. 4, the start transition in the received codeturns on a clock switch 103 which enables the clock 104 and an advancedriver 105 to feed clock pulses to the ring counter 106. The ringcounter 106 is of the same type as the ring counter described in theprevious example except that an extra stage has been added. Thisstart-stop stage is required to actuate the alarm after the lasttransition interval.

If the selector is adapted to recognize the code 1101, the outputs ofstages A, B, and D of the ring counter are connected in series to the ONinput of a bi-stable switch 107. The outputs of stages A, B and D arealso connected to a .95 bit delay switch 108. This delay switch can beof any well-known type which will delay the incoming pulse for .95 bit.

The output of delay switch 108 is connected to one input of an ANDcircuit 109 and to a delay line 110. The output of the delay line 110 isconnected to the OFF input 111 of the bi-stable switch 107.

The output of the inverter-differentiator 102 is fed to a delay line 112and to one input of an AND circuit 113. The output of the delay line L12is connected to the OFF input 111 of the bi-stable switch 107. The OFFoutput 114 of the bi-stable switch 107 is connected to the other inputto the AND circuit 113. The ON output 115 of the bi-stable switch 107 isconnected to the other input to the AND circuit 109.

The outputs of AND circuits 109 and 113 are the inputs to OR circuit116. The output of OR circuit 116 is connected to the OFF input 117 of asecond bi-stable switch 118.

The output of stage A of the ring counter is connected to the bi-stableswitch 118 so that bi-stable switch 118 will be turned ON only when a 1is shifted from stage A of the ring counter into stage B. When thisoccurs, an output will be transferred from stage A to the ON input 119of the bi-stable switch 118. The ON output 120 of bistable switch 1-18is connected to one input of an AND A circuit 121. The other input toAND circuit 121 is the output from stage D of the ring counter.Energization of both inputs to the circuit 121 will cause an output fromAND circuit 121 which will actuate an alarm 122 to indicate that theproper code has been received.

Operation of the selector of FIG. 4 is as follows: Before the code isreceived, a 1 is in stage A of the ring counter. The clock 104 andbi-stable switches 107 and 118 are OFF. The start transition in thereceived code turns on the clock switch 103 and enables the clock 104and advance driver 105 to feed clock pulses, shown in FIG. 5-3, to thering counter 106. The 1 is shifted by the first clock pulse from stage Ato stage B. When the 1 is shifted into stage B, an output pulse willappear on the series connected output windings as shown by the firstpulse in FIG. 5-4. This output pulse will turn on the bistable switch118 through the input 119. Bi-sta'ble switch 118 will remain on unless atransition in the received code occurs during an interval in which thereshould be no transition or if there is no transition in the receivedcode during an interval in which there should be a transition.

The time intervals, during which a transition must occur, are determinedby connections from the ring counter stages A, B, and D to the ONcircuit 123 of the bistable switch 107 and to delay switch 108. When thefirst clock pulse moves the 1 into stage B, bi-st-able switch 107 isturned ON by the first pulse shown in FIG. 54. The condition ofbi-stable switch 107 i shown in FIG. 5-6. Approximately .95 bit laterthe delay switch 108 pulses the AND circuit 109. FIG. -5 shows theoutput of delay switch 108. The delay switch 108 may have a delay ofbetween .5 bit and 1.0 bit so that the output of the delay switch occursbetween the next transition and the next clock pulse. If a transitionhas come in during this interval, bi-stable switch 107 has been turnedOFF through the input 111; hence, the AND circuit 109 will produce nooutput because there is no ON input to the AND circuit 109 frombi-stable switch 107. On the other hand, if the transition did not occurto turn OFF bi-stable switch 107, the pulse from delay switch 108 willpass through the AND circuit 109 and will turn the bi-stable switch 118OFF. If bi-stable switch 118 is turned OFF, actuation of the alarm atthe end of the ring counter cycle is inhibited.

The output from delay switch 108 is further delayed slightly by thedelay line 110 to reset bi-stable switch 107 OFF so that the sensing forthe desired transition is confined to the specific clock interval inwhich it should occur.

Sensing a transition in an undesired interval is accomplished asfollows: Bi-stable switch 107 will remain OFF during an interval inwhich the 1 has been shifted from one of the stages in the ring counterwhich is not connected to the ON input 123. If switch 107 is OFF, priorto the occurrence of any transition, that transition will pass throughthe AND circuit 113 to turn OFF bi-stable switch /118. Again, ifbi-st-able switch 118 has been turned OFF, the actuation of the alarm atthe end of the ring counter cycle will be inhibited.

Although a transition always turns OFF bi-stable switch 107, thetransition is delayed by the delay line 112 so that its operation onthat switch is delayed to permit AND circuit 113 operation prior tobi-stable switch 107 turnoff.

As the binary 1 passes from the start-stop stage of the ring counter, apulse on the output winding stops the clock through the OFF input 124 tothe clock switch 103. This pulse is also connected to one input to theAND circuit 121. If bi-sta'ble switch 118 has not been turned OFF, thepulse will pass through AND circuit 121 to actuate the alarm 122.However, if bi-stable switch 118 has been turned OFF, by the presence orabsence of a transition as described above, the alarm will not beactuated.

The number of different codes, which the selectors of the subjectinvention can distinguish, is limited only by the number of stages inthe ring counter. Each stage, which is added to the ring counter, allowsan additional bit to be added to the code which the selector is adaptedto recognize.

Reference to the following chart will show the binary codes which arepossible with a four-bit selector as shown in FIG. 1 or FIG. 4.

TABLE I The addition of each bit to the code will double the number ofpossible codes which can be distinguished.

The selectors of this application can be easily adapted for conferencecalling of two or more selectors with one code. The adaptation of theselector of FIG. 1 so that it will actuate an alarm in response to aconference call code as well as the specific code which the selector isadapted to recognize can best be explained with reference to Table Iabove showing the binary codes which are possible with a four-bitselector. The selector of FIG. 1, which is adapted to recognize the code1101, can be adapted to actuate the alarm on the reception of a example1001, by making a gating circuitry. The other selectors, which areadapted to recognize the codes 0001, 1011, and 1000, can also be adaptedto recognize the conference code 1001 in addition to the code which theyare particularly adapted to recognize. The selector of FIG. 1 can 'beadapted to recognize this conference code, as shown in FIG. 7, by simplyomitting the connection from the output of storage element B to the ANDcircuit 14, as for example, by opening a suitable switch. By omittingthis connection, the alarm of FIG. 1 will be actuated when either thecode 1101, which the selector is adapted to recognize or the conferencecode 1001, is received. As shown in FIG. 7, a ring counter 140, similarto ring counter 7 of FIG. 1, has a plurality of stages A, B, C, and D.The outputs from stages A and D are connected to an AND gate, not shown,corresponding to AND gate 14 of FIG. 1, and the output from stage C isconnected to an AND gate, not shown, corresponding to AND gate 13 ofFIG. 1. The output from stage B of the counter is not connected toeither of the AND gates as by opening switch 141 or by completelyomitting this lead. Thus, if the second bit is either zero (0) or a one(1), there is no output pulse from either of the AND gates, and thebi-stable switch is not actuated to inhibit actuation of the alarm.Thus, it can be seen that ring counter will respond to the binary code1001 or 1101. The outputs of these AND gates are connected to an ORgate, also not shown, corresponding to OR gate 15 of FIG. 1. This ORgate produces an output pulse in response to a pulse from either ANDgate which output pulse actuates a bi-stable switch, not shown, toinhibit an alarm gate to prevent the output pulse from stage D of ringcounter 140 from actuating the alarm.

The selector, which is adapted to recognize the code 0001, can also beadapted to recognize the conference code by omitting the connection fromthe output of the A stage of the gating circuits. Similarly, theselector adapted to recognize the code 1011 can be made to recognize theconference code by omitting the connection between the C stage and thegating circuitry and the selector adapted to recognize the code 1000 canbe made to recognize the conference code by omitting the connectionbetween the D stage and the gating circuitry. In the four-bit selectorshown, four selectors can be made responsive to a conference code aswell as to a particular code. The number of selectors, which can be maderesponsive to a conference code, depends upon the number of bits in thebinary code used. When fourteen bit selectors are used, for example, upto fourteen selectors can 'be made responsive to a conference code aswell as to a particular code.

Another advantage of the code selectors of this invention is the easewith which they may be adapted to error correcting. An error correctingsystem is desirable to insure that the selector is actuated in responseto a desired code even though one of the bits of the code is in errordue to faulty transmission. If the selectors are designed so that twoerrors must occur in the received code before actuation of the alarm isinhibited, the probability of a selector failing to actuate an alarm inresponse to a particular code is greatly diminished.

The amplitude sampling selector of FIG. 1 may be changed so thatactuation of the alarm is inhibited only when there are two errors inthe received code by inserting another bi-stable switch betweenbi-stable switch 12 and inhibit gate 9. This additional bi-stable switchwould be enabled by :bi-stable switch 12 being turned ON and would beturned ON by the output of OR gate 15. Thus, the alarm would beinhibited only after two or more errors in the received code. The numberof codes, which can be used out of the total number of possible codes,is somewhat limited when an error correcting system such as the onedescribed above is used. The selection of the codes, which are to beused to obtain the highest deconference call code, for very simplechange in the 11 gree of reliability, is discussed in detail in TheDesign of Switching Circuits, by W. Keister, A. E. Ritchie, and S. H.Washburn; chapter 12, section 12.4 of this book is particularlypertinent.

The selectors described above have been quite successful when used witha selective calling system. A fourteenbit selector was constructed usingtransistors and printed circuitry. The selector per-formed successfully.A fourteen-bit selector, such as this, is capable of recognizing one of16,384 codes which are possible when using a fourteen bit code.

The novel features believed descriptive of the invention are definedparticularly in the appended claims.

What I claim as new and desire to secure by Letters Patent of the UnitedStates is:

1. A code selector of the type used in the receiver of a selectivecalling system in which an alarm is actuated at a particular receiveronly when a particular binary code is received and recognized by theselector comprising a receiver line upon which is impressed a receivedbinary code consisting of a number of transitions between two inputconditions, a ring counter having a number of stages, means including asource of clock pulses for driving said ring counter through onecomplete cycle in response to the first transition of the received code,means for comparing the output from selected stages of the ring counterwith the received code on the receiver line to detect the presence of atransition in an undesired interval and the absence of a transition in adesired interval, an alarm, said alarm being actuated upon completion ofthe ring counter cycle only when there has been no transition in anundesired interval and no absence of a transition in a desired interval.

2. A code selector of the type used in the receiver of a selectivecalling system in which an alarm is actuated at a particular receiveronly when a particular binary code is received and recognized by theselector comprising, a receiver line upon which is impressed a receivedbinary code consisting of a number of time intervals, selected intervalscontaining a transistion between two input conditions, a ring counterhaving a number of stages, each stage corresponding to one time intervalin the received code, means including a source of clock pulses fordriving said ring counter through one complete cycle in response to thefirst transition of the received code, the outputs of. the stages of thering counter, which correspond to intervals in which a transition shouldoccur, being connected in series, a bistable switch, said bi-stableswitch being connected to said series-connected outputs, a first ANDcircuit, one output of said bi-stable switch being connected to said ANDcircuit, said AND circuit producing an output when there is a transitionin the received code in an undersired interval, a delay switch, saidseries-connected outputs being connected to said delay switch, a secondAND circuit, the output of said delay switch being connected to saidsecond AND circuit, a second output of said bi-stable switch beingconnected to said second AND circuit, said second AND circuit producingan output when there is an absence of a transition in a desiredinterval, an alarm, said alarm being connected to the last stage of thering counter, means for actuating said alarm upon completion of the ringcounter cycle only when said AND circuits have produced no output duringthe ring counter cycle.

3. A code selector of the type used in the receiver of a selectivecalling system in which an alarm is actuated at a particular receiveronly when a particular binary code is received and recognized by theselector comprising a receiver line upon which is impressed a receivedbinary code consisting of a number of transitions between two inputconditions, a ring counter having a number of stages, means including asource of clock pulses for driving said ring counter through onecomplete cycle in response to the first transition of the received code,the outputs of selected stages being connected in series, a delayswitch, said delay switch producing a delay between 0.5 and 1.0 bit, abi-stable switch, said outputs being connected to said delay switch andto the ON input of said bi-stable switch, a delay line, said receivedcode being connected to the OFF input of said bi-stable switch throughcaid delay line, the OFF output of said bi-stable switch being connectedto one input of a first AND circuit, the received code being directlyconnected to the second input to said AND circuit, a second AND circuit,the output of said delay switch being connected to one input of saidsecond AND circuit, the ON output of said bi-stable switch beingconnected to the other input to said second AND circuit, the outputs ofsaid AND circuits being connected to an OR circuit, the output of saidOR circuit being connected to the OFF input of a second bi-stableswitch, the ON output of said second bi-stable switch being connected toone input of a third AND circuit, the output of the last of said ringcounter stages connected to a second input to said third AND circuit, analarm, the output of said third AND circuit being connected to saidalarm for actuating said alarm.

References Cited UNITED STATES PATENTS 2,498,695 2/1950 McWhirter178--88 2,941,191 6/1960 Tyrlick 340-168 2,973,507 2/ 1961 Grondin340-164 NEIL C. READ, Primary Examiner.

D. YUSKO, Assistant Examiner.

1. A CODE SELECTOR OF THE TYPE USED IN THE RECEIVER OF A SELECTIVECALLING SYSTEM IN WHICH AN ALARM IS ACTUATED AT A PARTICULAR RECEIVERONLY WHEN A PARTICULAR BINARY CODE IS RECEIVED AND RECOGNIZED BY THESELECTOR COMPRISING A RECEIVER LINE UPON WHICH IS IMPRESSED A RECEIVEDBINARY CODE CONSISTING OF A NUMBER OF TRANSITIONS BETWEEN TWO INPUTCONDITIONS, A RING COUNTER HAVING A NUMBER OF STAGES, MEANS INCLUDING ASOURCE OF CLOCK PULSES FOR DRIVING SAID RING COUNTER THROUGH ONECOMPLETE CYCLE IN RESPONSE TO THE FIRST TRANSITION OF THE RECEIVED CODE,MEANS FOR COMPARING THE OUTPUT FROM SELECTED STAGES OF THE RING COUNTERWITH THE RECEIVED CODE ON THE RECEIVER LINE TO DETECT THE PRESENCE OF ATRANSITION IN AN UNDESIRED INTERVAL AND THE ABSENCE OF A TRANSITION IN ADESIRED INTERVAL, AN ALARM, SAID ALARM BEING ACTUATED UPON COMPLETION OFTHE RING COUNTER CYCLE ONLY WHEN THERE HAS BEEN NO TRANSITION IN ANUNDESIRED INTERVAL AND NO ABSENCE OF A TRANSITION IN A DESIRED INTERVAL.